// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2020 
// Author       : Haoxiaofei 
// Email        : 1531804419@qq.com
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 
// 
//
// *****************************************************************
module action_ram_pkt_4(
    input wire clka,
    input wire rst_n,
    input wire wea,
    input wire[4:0] addra,
    input wire[3:0] dina,
    output reg[3:0] douta,
    input wire clkb,
    input wire web,
    input wire[4:0] addrb,
    input wire[3:0] dinb,
    output reg[3:0] doutb
    );

// wire [4:0] addrb_1;    
reg[3:0] ram [31:0];
integer i;
//如果对同一地址进行写操作,只能写入A口数据
//如果对同一地址进行读和写操作，读出的数据为0,可以写入
always@(posedge clka or negedge rst_n)
  begin
    if(~rst_n)
      for(i = 0; i<= 31;i=i+1)
        ram[i] <= 40'h0;
    else if(wea && web)
      if(addra==addrb) 
        ram[addra] <= dina;
      else 
        begin
          ram[addra] <= dina;
          ram[addrb] <= dinb;
        end
    else if(wea)
      ram[addra] <= dina;
    else if(web)
      ram[addrb] <= dinb;
  end
always@(posedge clka or negedge rst_n)
  begin
    if(~rst_n)
      douta <= 40'h0;
    else if(wea)
      douta <= dina;
    else if(addra == addrb && web)
      douta <= 40'h0;
    else 
      douta <= ram[addra];
  end 

always@(posedge clkb or negedge rst_n)
  begin
    if(~rst_n)
      doutb <= 4'h0;
    else if(web)
      doutb <= dinb;
    else if(addra == addrb && wea)
      doutb <= 4'h0;
    else 
      doutb <= ram[addrb];
  end

endmodule